For expository convenience, the present invention is described with reference to one illustrative application thereof, namely a system for removing conversion errors in a subranging analog-to-digital conversion circuit (ADC). It will be recognized, however, that the invention is not so limited.
A typical subranging ADC 10 is shown in FIG. 1. It includes a track and hold circuit 12, first and second ADCs 14, 16, a digital-to-analog converter (DAC) 18, a load 20, an amplifier 22, and a summer 24. In operation, an input analog signal is applied to the track and hold circuit 12. The output from this circuit tracks its input until a clock signal applied thereto causes the circuit to momentarily hold its output fixed. The first ADC 14 then converts this analog output signal into digital form, thereby providing a first approximation of the digitized value.
The digital output from ADC 14 is converted back into analog current form by the DAC 18, causing an error, or residual voltage to be developed across the load 20. This residual voltage is amplified by the amplifier 22 and converted into digital form by the second ADC 16. The accuracy of ADC2 is less critical than ADC1 since it is only operating on the residual or "subrange" of the original signal. In the FIG. 1 system, the errors of ADC2 are only one 64th as significant as errors in ADC1.
The summer 24 sums ADC1's first approximation of the input analog signal and ADC2's representation of the residual (appropriately adjusted for the gain of the amplifier) to provide a composite digital output signal.
The advantage of the subranging approach is that the accuracy of the result is dependent only on the accuracy of the DAC and ADC2, not on the accuracy of ADC1. The size of the residual is still a function of ADC1 accuracy but the accuracy of the residual is not. This shifts the primary accuracy requirements to the DAC instead of the ADC, taking advantage of the inherently higher accuracy of DACs for a given sample rate.
The principal limit on accuracy in subranging ADC 10 is the accuracy with which the DAC 18 converts the digital output of ADC1 14 back into analog form. The DAC 18 typically generates its output signals by controllably gating binarily weighted currents into a summation node in response to the bits of the digital input signal. The magnitudes of these component current sources are set by resistors internal to the DAC. High accuracies can be achieved by laser trimming each resistor in each DAC to achieve a desired measure of accuracy. However, such custom processing makes the DAC expensive and thus unsuitable for many applications. Mass produced DACs are much less expensive but can significantly compromise the accuracy of a subranging ADC.
To permit use of mass produced DACs in subranging ADCs, a technique has been developed wherein the error of each of the DAC current sources is quantified, and the resulting subranging ADC output signal is compensated for their cumulative error. FIG. 2 shows such a system. The correction circuit 26 includes a memory in which the error of each of the DAC's current sources is stored. By monitoring the digital signal applied to the DAC, the correction circuit 26 can determine the current sources that are active, calculate their cumulative error, and subtract this error from the final subranging ADC output signal.
While the foregoing technique provides high accuracy without precision DACs, it requires a calibration cycle in which each of the DAC current sources is individually operated, its output current compared against ideal reference values to quantify its error, and the error terms stored. One difficulty with this procedure is that of obtaining the requisite ideal reference values. More troublesome is the fact that the DAC errors change with age, temperature, and a variety of other factors, requiring recalibration periodically if accurate results are to be achieved.
To overcome these difficulties, the present invention provides a technique wherein the errors of the component DAC current sources are determined automatically during the circuit's normal operation. This is achieved, in a preferred form of the invention, by continually introducing a random signal into the process, statistically examining the DAC output signal to discern error terms, and correlating the occurrences of these errors with the values of the random signal applied to the DAC so as to identify the current sources to which the error terms are due. The resulting output signal is compensated to remove the random signal and is further compensated to remove the DAC error terms discerned by this statistical analysis.
The effect of any errors that may remain due to imperfect quantification of the DAC error terms is minimized because these errors are now random, permitting them to be removed by averaging techniques.
The foregoing and additional features and advantages of the present invention will be more readily apparent from the following detailed description thereof, which proceeds with reference to the accompanying drawings.